As shown in the partial sectional view of FIG. 1A, the conventional typical LOCOS process is carried out in the following manner. That is, a pad oxide layer 12 is formed on a semiconductor substrate 11, and then, a silicon nitride layer 13 is deposited thereupon. Then an isolating region (field region) is patterned by applying a photo etching method. Thereafter, a field oxidation process is applied to grow a thick field oxide layer.
Then, as shown in FIG. 1B, the nitride layer 13 is removed, and then, the pad oxide layer 12 is removed. Then a sacrificial oxide layer is grown, and this is etched, thereby forming a structure of FIG. 1C.
Through such a process, an element forming region and an element isolating region, i.e., an active region and a field region are separated from each other on a semiconductor substrate, and then, a gate oxide layer, a gate electrode and a source/drain region are formed, thereby completing a transistor.
In this conventional method, after the field oxide layer is formed, the oxide layer is etched two times, and therefore, a considerable portion of the filed oxide layer is removed, this becoming a problem. In actual, prior to growing the gate oxide layer, the sacrificial oxide layer has to be completely removed, and therefore, an excessive etching is done, with the result that the etched amount of the field oxide layer is increased far too much. Consequently, the corners of the isolating region is recessed and exposed, with the result that the electrical characteristics are aggravated (junction leakage, oxide breakdown and the like).
Further, in the conventional typical LOCOS process, a thick field oxide layer is grown by much more than necessary, and therefore, stress occurs to generate defects.
Further, after the growing of the field oxide layer, the etching is carried out by two times (etching of the pad oxide layer and the sacrificial oxide layer), and therefore, a considerable amount of the field oxide is removed. Therefore, the field oxide layer has to be formed thick at the initial stage. Further, due to the excessive etching, the silicon portions of the corners of the isolating region is dug into the active region, and therefore, the electrical characteristics are aggravated. Further, the field oxide layer which is disposed vertically relative to the gate may be considerably removed during an etching for forming an oxide side wall for an LDD.